1. Field of the Disclosure
The present disclosure relates to a gate driving unit and a liquid crystal display (LCD) device having the same, and particularly, to a gate driving unit capable of having reduced design area and power consumption by reducing an off-time of a gate signal, and an LCD device having the same.
2. Background of the Disclosure
As an information society develops, demands for a display device for displaying images increase. The display device includes various types of flat display devices such as a liquid crystal display (LCD) device, a plasma display panel (PDP) device and an organic light emitting diode (OLED) device.
Among such flat display devices, the LCD device is being widely used due to its small size, light weight, small thickness, driving with low power consumption.
The LCD device is configured to display images by controlling light transmittance of liquid crystals having dielectric anisotropy, using an electric field.
Such LCD device includes a gate driving unit configured to receive control signals from a timing controller (not shown) to thereby generate gate signals, and configured to sequentially supply the generated gate signals to gate lines (not shown) to thereby turn-on TFTs connected to the gate lines; a data driving unit configured to receive control signals and image signals from the timing controller, and to thereby apply data voltages corresponding to the image signals to data lines (not shown); and a timing controller configured to control the gate driving unit and the data driving unit.
FIG. 1 is a view showing a gate driving unit of an LCD device in accordance with the conventional art.
As shown in FIG. 1, the gate driving unit (not shown) includes a shift register 20 and a dummy stage circuit unit 22. Here, the shift register 20 including N stage circuit units which operate by receiving a start signal (not shown) and first to fourth clock signals (CLK1˜CLK4) from a timing controller (not shown). The gate driving unit outputs gate signals to a preset number of gate lines.
The (N−1)th stage circuit unit receives a start signal (not shown), first and second reset signals (RST_odd, RST_even), and first and second clock signals (CLK1, CLK2), thereby outputting first and second gate signals (Gout(N−1)_0, Gout(N−1)_E) to first and second output terminals (Vout_odd, Vout_even).
As the first and second reset signals (RST_odd, RST_even), input are gate signals (Gout(N)_E) applied to an Nth even-numbered gate line output from the Nth stage circuit unit.
The (N−1)th stage circuit unit includes two stage circuit units therein. The (N−1) stage circuit unit 1 (not shown) outputs a first gate signal (Gout(N−1)_0) applied to an (N−1)th odd-numbered gate line, and the (N−1) stage circuit unit 2 (not shown) outputs a second gate signal (Gout(N−1)_E) applied to an (N−1)th even-numbered gate line. The first gate signal and the second gate signal are sequentially output with a time interval.
The dummy stage circuit unit 22 receives a second clock signal (CLK2) from the outside, thereby outputting a dummy gate signal (Gout_D). And, the dummy stage circuit 22 receives a reset signal (RST) applied from the outside as a reset signal (RST_D), thereby outputting a gate off signal.
FIGS. 2 and 3 are views respectively showing a gate signal of a pull-up transistor inside an (N−1)th stage circuit unit, and FIG. 4 is an enlarged view of part ‘A’ in FIG. 2.
As shown in FIGS. 2 to 4, the (N−1)th stage circuit unit includes therein a first pull-up transistor (not shown) for receiving a first clock signal (CLK1) and outputting a first gate signal (Gout(N−1)_0) to a first output terminal (Vout_odd), and a second pull-up transistor (not shown) for receiving a second clock signal (CLK2) and outputting a second gate signal (Gout(N−1)_E) to a second output terminal (Vout_even).
As shown in FIG. 2, as first and second off signals (V1, V2) for turning off the first and second pull-up transistors are simultaneously input to gates of the first and second pull-up transistors, voltage wavelengths of the first and second off signals (V1, V2) are asymmetric to each other.
As shown in FIG. 3, there are holding periods (a, b) where a prescribed voltage is maintained for a prescribed time when the first and second off signals (V1, V2) are discharged. In the holding periods (a, b), the first and second gate signals ((Gout(N−1)_0), (Gout(N−1)_E)) output from the (N−1)th stage circuit unit are asymmetric to each other, due to a voltage difference between the first and second off signals (V1, V2) and asymmetric operations of the first and second pull-up transistors. The reason is because a voltage of the second off signal (V2) with respect to the first off signal (V1) is lowered in the holding periods (a, b), and thus signals output from the second pull-up transistor become weak.
Further, as shown in ‘A’ of FIG. 4, the gate driving unit operates with receiving bias temperature stress (BTS). As an output characteristic is degraded due to a long driving of the gate driving unit, a voltage of the second off signal (V2) may be lowered in the holding periods. This may result in an abnormal driving of the LCD device. Here, c indicates a second off signal (V2) before the gate driving unit is driven at a high temperature (e.g., 60° C.), and c′ indicates a second off signal (V2) after the gate driving unit is driven at a high temperature (e.g., 60° C.) for 1000 hours.